Terminators

The following catalog products are recommended for new applications. If the product required is not shown, we may have a customized product for your application. Please contact your CTS Representative for availability.

This product is covered by one or more of the following U.S. and foreign patents:
US 5,977,863; TW NI-133,148; US 6,005,777; US 6,097,277; US 6,194,979; TW NI-141,800; US 6,246,312; US 6,326,677; US 6,577,225;
US 6,749,775; US 6,856,516; US 6,882,266; US 6,897,761; US 6,946,733; US 6,963,265. -- Other U.S. and foreign patents pending.
 

Application Picture Configuration Description
       
LVD SCSI

ROHS
Style E

9 line differential terminator set designed to meet Ultra2 and Ultra 3 LVD SCSI standards.

DDR SDRAM

ROHS
Style H

9 line integrated terminator set provides series termination at the source and parallel termination at the receiver. Designed to meet Jadec Std. 8-9a.+/- 1% tolerance.

Style F

Style C
Compact PCI,

ROHS

IDE, DRAM, SDRAM

ROHS
Style C

16 line or 32 line terminator provides series termination at the source. Designed for CompactPCI PC card and memory applications. Standard resistance tolerance +/-1%
GTL

ROHS
Style D

8, 16 or 32 line terminator provides parallel termination at the receiver. Designed with star pattern to minimize crosstalk and improve high frequency performance. Tolerance +/- 1%
PCI

ROHS
Style F

8 or 16 line bias network provides pull-up or pull-down to reference voltage. Designed for PCI and PCIX applications. Standard tolerance +/-1%
LVPECL

ROHS
Style G

8 line terminator network provides Thevenin termination. Designed for LVPECL applications. Standard resistor tolerance is ±1%
VME

ROHS
Style G

8 line terminator network provides Thevenin termination. Designed for VME64 and VME64x applications. Standard resistance tolerance is +/-1%
FPGA/LVDS

ROHS
Style C

These LVPECL and LVDS termination networks are designed for high performance termination of differential Input/Output signals on some of the most popular Field Programmable Gate Arrays (FPGAs).  Designed for termination of Xilinx® and Altera® FPGAs.  8 or 16 differential channels of termination provided in a single integrated package.

Style I

 

ClearONE Resistor/Capacitor Ball Grid Array Package
R/C BGA

This Resistor/Capacitor terminator network provides high performance termination.

Designed with a ceramic substrate, this device virtually eliminates channel capacitance, a primary cause of reduced system performance.  In addition, the BGA package eases routing design, saving the designer many hours of printed circuit layout.

 

ClearONE Topside Probable Diagnostic Parts

Topside Probable Parts

In general, all ClearONE designs can be made available in Top Probe-Able versions upon request.  Many of the standard products are available off-the-shelf, but your local CTS ClearONE representative should be contacted for specific device ordering and availability details.  Figure 1 describes the proper numbering to convert a standard ClearONE part number to the Top Probe-Able version.  (See Topside Probable Application Note for more information.)



Figure 1
DIM
Metric/English		 "Pitch Suffix"
B6 B7
"A" 0.64/.025 0.50/.020
"B" 1.27/.050 1.00/.039
"C" 0.64/.025 0.50/.020
"D" 0.66/.026 0.50/.020
"E" 0.71/.028 0.28/.011
"F" 0.66/.026 0.66/.026

Figure 2 — Probe Pad Layout